1. Field of the Invention
The present invention relates to a method of manufacturing a ferroelectric memory, and more particularly, to a method of manufacturing a ferroelectric memory by which an insulating layer and a ferroelectric layer are stacked on a substrate, and the diffusion and absorption of the insulating layer into the ferroelectric layer are controlled, and thus a metal/ferroelectric/silicon (MFS) or metal/ferroelectric/insulator/silicon (MFIS) structure is formed, and by which undesirable reaction may be prevented at an interface between the ferroelectric material and a silicon substrate.
2. Description of the Related Art
Ferroelectric materials have attracted considerable attention for their application to non-volatile memory devices. In general, circuits using two transistors and two capacitors (2T2C) cells or one transistor and one capacitor (1T1C) cells are conventionally used for ferroelectric memory cells. A memory with ferroelectric floating gate field effect transistor (FET), named MFMIS (Metal/Ferroelectric/metal/Insulator/Semiconductor), has been suggested as a new type ferroelectric nonvolatile memory, in which a surface inversion layer is generated by the charge induced by the polarization of ferroelectric floating gate. Such a cell has several advantages, including a non-destructive read out and simple high-level integration due to 1Tr cell. However, considerably high operation voltage is required to overcome a voltage drop caused by the insulating layer.
Ferroelectric memory FET having a metal/ferroelectric/semiconductor (MFS) structure solve this problem. However, if the ferroelectric layer such as lead zirconate titanate (PZT) is deposited directly on a silicon substrate, diffusions of Pb, Ti and other elements into silicon substrate take place to form unnecessary phases such as silicate or silicide, so that it is impossible to manufacture a desired MFS type 1Tr memory cell.
FIG. 1 is a sectional view of a MFS-type ferroelectric memory.
Referring to FIG. 1, a ferroelectric PZT layer 12 is deposited on a silicon substrate 11, and a metal electrode 13 is formed on the ferroelectric layer 12.
In the MFS-type ferroelectric memory, a chemical reaction occurs between the ferroelectric layer 12 and the substrate 11 during deposition of the PZT layer 12, and thus undesirable substances such as silicate or silicide are generated at the interface of the ferroelectric material and the silicon. Here, the silicide is conductive, and thus a short may occur between a source and a drain. Also, because the silicate is a low dielectric material, it causes voltage drop problem described later. In case of using other ferroelectric materials such a SrBi.sub.2 Ta.sub.2 O.sub.9, CaBi.sub.2 Ta.sub.2 O.sub.9, Bi.sub.3 TiNbO.sub.9 or Bi.sub.4 Ti.sub.3 O.sub.12, similar reactions at the interface between the ferroelectric and substrate may occur, deteriorating ferroelectric characteristics and creating problems in FET operation.
Accordingly, as shown in FIG. 2, a metal/ferroelectric/insulator/silicon (MFIS) structure has been proposed to prevent undesirable reaction, where an insulating layer 22 is interposed between a substrate 21 and a ferroelectric layer 23. Reference numeral 24 indicates a metal electrode. Here, the insulating layer 22 is a buffer layer for preventing the chemical reaction. However, similarly to the MFMIS structure, the MFIS has two layers of insulating material connected in series, so that the operation voltage is shared between the ferroelectric layer 23 and the insulating layer 22, and the voltage available to the ferroelectric layer is less. Therefore, a higher operation voltage is required for operating the MFIS-type 1Tr than for the MFS. To avoid this, the thickness of the insulating layer 22 must be reduced to lower the voltage drop across the insulating layer 22. The thickness of the insulating layer can be most easily reduced during deposition. However, when the initial deposition thickness is 150 .ANG. or less, the layer is unstable due to poor deposition technique and thus it is difficult to obtain a reproducible and stable device.